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Features
* Contactless Interface
- Reads and Writes Passive RFID Tags in the Unlicensed 13.56 MHz Band - Employs ISO/IEC14443 Type A Modulation Schemes - Autonomous Operation Capability (can scan and read tags without host intervention - i.e. only passes data following successful read/write operation) - Compatible with NFC Initiation Only Device - User Has Control Over Initiation of all RFID Based Services and Features - Read/write Operation Between 1 cm and 10 cm Read Range, Depending on Reader/Tag Antenna Coil Sizes and Orientation Relative to the Reader - Collision Detection as Standard - Transparent Modes for Software Controlled Modulation Supports Maximum Flexibility and Future Protocols - Fast Data Communication Rate of 106 kbit/s - Suitable for Operation with a Wide Variety of Antenna Coil Sizes and Form Factors - Four Software Adjustable Carrier Field Drive Levels Controller and Software - On-board Powerful Atmel AVR(R) RISC microcontroler, programmed with Innovision(R) proprietary software. - Built in Self Test and Diagnostic Modes - Internal 8 MHz RC Oscillator for Micro or External Crystal Operation Host Interface - 3-wire SPI Interface as Standard - Full Software Control via SPI bus at 115 Kbaud as Standard Interface Power Supply - Ultra Low Current Operation and Stand-by Sleep Mode Typically < 1 A - Ultra Low Voltage Operation: 2.7V - 3.3V Additional features - Packages: LBGA36 - LBGA Requires Only an External Crystal, 10 Passives and the Reader Antenna Coil - Operating temperature range: -30C to +80C
*
* * *
Integrated 13.56 MHz Contactless Reader with Embeded software AT90RF135602
Description
AT90RF135602 is an ultra small footprint low-cost Radio Frequency Identification (RFID) reader developed with Innovision Research & Technology plc to address multi-protocol 13.56 MHz RFID applications. It is optimised for use with the established ISO/IEC14443 type A standard and is available in Low-profile Ball Grid Array (LBGA). The LBGA incorporates a custom transceiver front-end along with a protocol & communications controller. It requires only an external crystal and minimal external passive components to interface to the reader antenna. Protocols are software defined and hence configurable.
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Benefits
* * * * * * * *
Low-cost - ideal for RFID applications where costs have traditionally proved prohibitive Ultra miniature footprint for compact reader design Low voltage operation ideal for rechargeable and/or portable applications Low operating current for optimal power utilisation Low quiescent current sleep mode further prolongs battery life of applications Easily integrated into host reader system Scalable on-board processor memory size and capacity for custom design solutions Operation with multiple protocols such as Philips Mifare(R) Ultralight, Innovision(R)-R&T JewelTM and ISO/IEC14443 type A tags ensures multi-platform compatibility and seamless integration into legacy systems Software performs mapping between a common logical memory structure model and physical memory maps of multiple tags types Also operates with Innovision R&T proprietary protocols and transparent reader modes for even lower power consumption levels Powerful on board RISC processor is available to operate at higher levels of application protocol stack than on conventional reader solutions for more autonomous modes of operation Passive read/write RFID tag applications operating in the unlicensed 13.56 MHz band Hand-held and low-power battery operated ISO/IEC 14443 type A read/writers Reader to reader inductive/Near Field Communications
* * *
Applications
* * *
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Block Diagram
The host system, typically containing an application microprocessor, can control the operation of the AT90RF135602 by interfacing commands and application data over a bi-directional Serial Peripheral Interconnect (SPI) interface.
Figure 1. Typical System Architecture
Low Profile Ball Grid Array (LBGA)
Host
SPI
Micro Controller
RF Reader
Passive
Antenna Coil
Regulator (2.8V)
13.56 MHz Xtal
The partitioning of the system into its typical protocol layers is shown in Figure 2. The exact boundary of each layer of the protocol stack is dependent on the specific application and, therefore, the optimal architectural split of the protocol layers. Software implementation of the protocol stack allows for operation with multiple parallel stacks as well as greater flexibility for customisation and future updates.
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Figure 2. Overview of Typical Protocol Layers based on OSI 7-layerModel
Host Micro
Scan/Read/Write Commands, etc.
Application Layer
Transmission Protocol
Innovision R&T JewelTM Mifare(R) Ultralight Protocol
ISO14443 part 3 Reader Micro Intialisation & Anti-collision
Frame Format & Timing
ISO14443 part 3
Bit Representation & Timing Reader ASIC Modulation
ISO14443 part 2
ISO14443 part 2
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Pinout
Figure 3. LBGA36 Package Pinout
F E D C B A
1 PC4 SCK MISO (SDO) MOSI (SDI) /SS XTAL2
2 VDDQ VCC2 VDD01 VDD02 GND1 XIN 3 PC6 VCC1 GND2 /Reset (/MCLR) 4 PC7 XOUT 5 TX1 XTAL1 6 PD1 VDD VSS PC5 7 Substrate Substrate VSS02 VSS01 VSSQ TX2 8 PDO PC3 PC2 RX PC1 PC0
Pin Description
Table 1. AT90RF15602 Pin Description
PIN Name VDDQ VDD VDDO1 VDDO2 VCC1 VCC2 Pin Number F2 E6 D2 C2 E3 E2 i/0/p Type Power Power Power Power Power Power Description Analogue Supply Logic Supply Output Stage Supply Output Stage Supply MCU Supply MCU Supply
GND1 GND2 VSS VSSQ VSSO1 VSSO2
B2 B3 B6 B7 C7 D7
Power Power Power Power Power Power
MCU GND MCU GND Logic GND Analogue GND Output Stage GND Output Stage GND
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Table 1. AT90RF15602 Pin Description (Continued)
PIN Name Substrate 1 Substrate 2 Pin Number F7 E7 i/0/p Type Power Power Description GND GND
/SS MOSI (SDI) MISO (SDO) SCK /RESET (/MCLR) PD0 PD1
B1 C1 D1 E1 A3 F8 F6
Input Input Output Input Input
SPI Slave Select (Active Low) * SPI Data Input * SPI Data Output * SPI Clock * Reset (Active Low) RESERVED RESERVED
PC0 PC1 PC2 PC3
A8 B8 D8 E8
RESERVED RESERVED RESERVED RESERVED
PC4 PC5 PC6 PC7 TX1 TX2 RX XIN XOUT XTAL1 XTAL2
F1 A6 F3 F4 F5 A7 C8 A2 A4 A5 A1 Output Output Input Input Output
RESERVED RESERVED RESERVED RESERVED Antenna Drive 1 Antenna Drive 2 Antenna Receiver 13.56 MHz Crystal or CLK input 13.56 MHz Crystal or N/C RESERVED RESERVED
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Definition of Terms
ASIC BIST CRC CSUM ETSI FCC Fc FIFO Fs GUI TWI LBGA OTP PC PCD PCB PICC RAM SPI TBA TBC UART XTAL
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Application Specific Integrated Circuit Built In Self Test Cyclic Redundancy Check Check Sum European Telecommunication Standards Institute Federal Communications Commission Frequency of Carrier First In First Out Frequency of Subcarrier Graphical User Interface Two Wires Interface Low-profile Ball Grid Array One Time Programmable Personal Computer (IBM compatible) Proximity Coupling Device Printed Circuit Board Proximity Integrated Circuit Card Random Access Memory Serial Peripheral Interconnect To Be Advised To Be Confirmed Universal Asynchronous Receiver Transmitter Quartz Crystal
Functional Specification
Outline Functional Specifications
The major determination of the functionality is the embedded software. The following specification is designated for the latest V2.7 software release. The AT90RF135602 is designed to achieve the following requirements:
Passive RFID reader operation in the unlicensed 13.56 MHz band Read/Write operation using ISO/IEC14443-2 type A modulation schemes at data communication rates of 106 kbit/s Conform to the standard of ISO/IEC14443-3 type A as far as is required to operate with the Mifare Ultralight and the Innovision R&T low-cost Jewel RFID ICs Low voltage operation from a 2.7V supply Low current operation with stand-by sleep mode Interface electrically to the host system controller via an SPI based interface and associated digital control signals Operates with minimal battery power consumption to optimise the battery life in both active and standby modes Operation with Innovision R&T low-cost, low power proprietary tag protocols
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Reader to reader inductive Near Field Communications capability using Innovision R&T proprietary protocols in software Transparent modes for direct software controlled modulation protocols for maximum flexibility
General Specifications
*
Multi-protocol RFID IC: - - ISO/IEC14443A parts 2 & 3 (frame format) User transparent operation with both the Philips Mifare Ultralight and Innovision R&T low-cost Jewel tags
* *
Operation:Read/Write Number of bytes: - - Ultralight: 48 user Read/Write bytes Jewel: 96 user Read/Write bytes
* * *
Tag scan rate:Variable by host Carrier frequency:External 13.56 MHz crystal controlled Carrier field drive level: - Four software adjustable carrier field drive and Q levels determined by selection of output stage drive impedance: Level1 - 40 Level2 - 20 (Default for v2.7) Level3 - 10 Level4 - 5
*
Antenna configuration:Balanced "push-pull" output stages driving a symmetrical series resonant antenna coil for optimal carrier field generation when operating from low voltage supply FCC/ETSI EMC Compliancy:Simple LC low-pass filters used on output stages to achieve harmonic reduction required for EMC compliancy Operating voltage range: 2.7 - 3.0 V Maximum voltage rating: 3.3 V Peak supply current: < 65 mA peak (depending on drive level selection, antenna matching and tuning) Sleep-mode quiescent current: <10 A (1 A typical) Protocol Control: Atmel pre-programmed RISC Microprocessor Software program memory: Pre-programmed with Innovision Firmware revision V2.7 Data memory: Reserved Non-volatile memory: Reserved Interfaces: - 3 wire SPI interface at 115 kBaud
* * * * * * * * * *
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Figure 4. Recommended Circuit for Extended Range
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Figure 5. Recommended Circuit For Short Range Application
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SPI Interface Protocol
Serial Peripheral Interface - SPI
Features The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90RF135602 and peripheral devices or between several AVR devices. The AT90RF135602 SPI includes the following features: * * * * * * * *
Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode
Figure 6. SPI Block Diagram
clk IO
DIVIDER /2/4/8/16/32/64/128
SPI2X
SPI2X
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 7. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out - Slave In, MOSI, line, and from Slave to Master on the Master In - Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 7. SPI Master-slave Interconnection
SHIFT ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed fclkio/4.
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General
This section describes the operation and interface protocol between the typical host controller and the AT90RF135602 for v2.7 of software. The AT90RF135602 always operates as a slave to the host controller device acting as the master. The SPI interface operation is specified by the /SS and /RESET lines as shown in the table below.
/RESET Low High High
/SS Low or High High Low
Interface Mode Reserved Sleep mode SPI interface and AT90RF135602 active
To clarify: The AT90RF135602 ignores SCK from the host and tri-states the MOSI and MISO lines whilst /SS is high As the slave, the AT90RF135602 accepts the SCK from the host and produces serial output data from its MISO output only when /SS is low. The MOSI input is used to receive commands and data from the host in conjunction with the SCK clock when /SS is low. Operation from a cold power-up and reset defaults to be in low quiescent current "Sleep Mode" waiting for /SS to go low.
SPI Setup
AT90RF135602 is slave. /SS idle condition is high. Prior to transmitting a message the /SS line is set low by the host, after the message has been transmitted the /SS line is set back high again. The interval between the host lowering /SS and then generating the first SCK pulse should be a minimum of 3us. SCK idle condition is low. The leading edge is rising and the trailing edge falling. In each direction data is loaded on the rising clock edge and is valid (and sampled) on the falling clock edge. The minimum interval between the 8th SCK of a byte and the 1st SCK of the next byte shall be 10us for status poll commands and 23us for all other commands.
SPI Command/Response The host generates the SPI clock signals to send "Command" messages to the AT90RF135602. Message Structure
The host generates the SPI clock signals to receive "Response" messages from the AT90RF135602. The generic message structure is independent of message direction and is transparent to the SPI hardware interface.
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Messages are either single byte or multi-byte. All messages are terminated by an 8-bit Checksum byte (CSUM) this is calculated as the 8-bit sum of all the proceeding bytes in the message. Multi-byte messages are indicated by the most significant bit set to "1" in the first byte of the message. The length of the additional information is determined by the message type and nature of the additional information bytes. The maximum allowable length of a message including its checksum is 255 bytes.
SPI Message Type 1st Byte Single byte message
Byte 0x00 - 0x7F
Description
Single byte message type (1 byte + Checksum) 2nd Byte CSUM 0x80 - 0xFF 1st Byte Multi-byte message type Multi-byte message (Minimum of 3 bytes + Checksum) 2nd Byte 3rd Byte 0 - 251 Bytes Last Byte Information byte Information byte Additional information bytes CSUM
The host may command Read/Write to the whole of a tag or can restrict the operation to individual pages and sectors using a common message structure which can be independent of tag type.
Addressing Modes
The v2.7 AT90RF135602 software provides for two modes of addressing tags using either Logical or Physical addressing depending on the command variant. For Logical addressing the application can work independent of tag type as long as the data capacity is not exceeded. The AT90RF135602 software will seamlessly handle the mapping of logical addresses over to either the Innovision Jewel or the Philips Mifare Ultralight depending on the type of tag it recognises as being present. The mapping for logical start address is given in Appendix A. For Physical addressing the application layer must first know which type of tag is present and then address the memory bytes using physical addresses from the tag datasheet. The user is referred to relevant datasheet documentation.
AT90RF135602 Command Message Structure
To wake-up the AT90RF135602 and to start the tag read or write operations the host as the master must send either a single or a multi-byte Command message. The single byte message consists of a command byte and checksum byte, as follows: To AT90RF135602 =
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The multi-byte message consists of a command byte, start address byte, data length value byte, the data (if relevant to the command) and checksum byte as follows: To AT90RF135602 = ..... Where: - is the command byte with top bit set (e.g. Read, Write, etc)
- is the start address byte (0 to 255) for the operation* - is the length in number of bytes to read or write (0 to 240) - is data byte(s) - sent least significant byte first - if relevant to the command (e.g. for writing) - is the 8-bit sum of the proceeding bytes The message is sent most significant byte (i.e. byte) first. The data bytes are sent least significant byte first. The 8-bit bytes are sent MOST significant bit first. Subsequent to a command message (which both wakes-up the AT90RF135602 and starts the tag read or write operations) the host as the master should poll periodically to assess the status and progress of the commanded operation. * Start address is given in logical terms for user Read/Write area (see Appendix A)
Table of Commands
Explanation Poll Status from AT90RF135602 Built-In Self Test 0x70 (See Built-In self test section for further details) = 0x00 = 0x00 = 0x70 = 0x00 = 0x80 Read User Data Logical (Read requested number of user R/W data bytes from requested logical start address of any tag type) 0x80 Read Physical (Read requested number of bytes from requested physical start address of known tag type) 0x86 NB Application must know tag type = Start logical address = Number of bytes to be read = Checksum User data starts at logical address 0x00 = 0x86 = Start physical address = Number of bytes to be read = Checksum = 0x90 = Start logical address = Number of bytes to be read Read UID/lock/OTP/User Data logical (Read requested number of UID, lock, OTP & user data bytes from requested logical start address of any tag type) = Checksum UID starts at logical address 0x00 to 0x07 Lock bits start at logical address 0x08 to 0x09 OTP bits start at logical address 0x0A to 0x0F 0x90 User data starts at logical address 0x10 Bytes
0x00
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Explanation = 0xA0 = Start logical address Write User Data Logical (Write requested number of user data bytes starting at requested logical address of any tag type)
Bytes
= Number of bytes to write (n) ... = n bytes to write = Checksum User data starts at logical address 0x00 = 0xA4 = Start logical address
0xA0
Write User Data Logical to specific UID (Verify specific UID; if equal then write requested number of data bytes starting at requested logical address and verify, if still present) 0xA4 Write Physical (Write requested number of bytes starting at requested physical address of known tag type and verify, if still present) NB: Application must know tag type
= Number of bytes to write (n) ... = UID of specified tag ... = n bytes to write = Checksum User data starts at logical address 0x00 = 0xA6 = Start physical address = Number of bytes to write (n) ... = n bytes to write = Checksum
0xA6
= 0xA8 Write Physical to specific UID (Verify specific UID; if equal then write requested number of bytes starting at requested physical address of known tag type and verify, if still present) NB: Application must know tag type 0xA8 User data starts at logical address 0x00 Configuration data - 3 bytes 0xAC010020 - selects 40 Driver resistance 0xAC030020 - selects 20 Driver resistance 0xAC050020 - selects 10 Driver resistance Reader IC Configuration diagnostic command 0xAC070020 - selects 5 Driver resistance This setting remains in force for subsequent communications with the tag until the AT90RF135602 is reset. 0xAC The default driver resistance after reset or power up is 20 for software v2.7. = 0xB0 = Start logical address Write Lock/OTP/User Data logical (Write requested number of lock, OTP & user data bytes to requested logical start address of any tag type and verify, if still present) NB: Writing to UID area is not valid 0xB0 = Number of bytes to write(n) ... = n bytes to write = Checksum UID starts at logical address 0x00 to 0x07 Lock bits start at logical address 0x08 to 0x09 OTP bits start at logical address 0x0A to 0x0F User data starts at logical address 0x10 = Start physical address = Number of bytes to write (n) ... = UID of specified tag ... = n bytes to write = Checksum
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Explanation = 0xB4 = Start logical address
Bytes
= Number of bytes to write(n) Write Lock/OTP/User Data Logical to specific UID (Verify specific UID of tag; if equal then write requested number of lock, OTP & user data bytes to requested logical start address of any tag type and verify, if still present) NB: Writing to UID area is not valid. ... = UID of specified tag ... = n bytes to write = Checksum UID starts at logical address 0x00 to 0x07 Lock bits start at logical address 0x08 to 0x09 OTP bits start at logical address 0x0A to 0x0F 0xB4 User data starts at logical address 0x10
See Appendix B for an example Command Response sequence.
AT90RF135602 Response Message Structure
At the same time as the host sends a message, the AT90RF135602 returns its status response: Single byte response from AT90RF135602 = If the AT90RF135602 is still busy processing the last command then the response data received during the 16 clock periods of the polling command message will be: STATUS = 0x01 which means AT90RF135602 busy. When the AT90RF135602 has finished its operation, or has error conditions, then either a single byte or a multi-byte status message will be returned by SPI clocks from the host. Multi-byte response from AT90RF135602 = Where: - Status response
- Status byte 1 which includes further information (e.g. tag type from the previous operation) - is the length in number of bytes that were successfully read or written (0 to 240). It is only present if relevant to the status response. - is data byte(s), if relevant to the command (e.g. for reading) - is the 8-bit sum of the proceeding bytes The message is sent byte first. The data bytes are sent least significant byte first. The 8-bit bytes are sent most significant bit first.
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Table of Responses
Single Byte Responses 0x00 0x01 0x10 0x20 Explanation Normal operation
The checksum byte is not shown in the table below.
Bytes = 0x00 = Checksum = 0x01 = Checksum = 0x10 = Checksum = 0x20 = Checksum
Busy processing last command SPI Command Format Error No Tag Found
Multi-byte Responses 0x80 Explanation Read User Data Logical Successful Bytes = 0x80 = tag type = number bytes successfully read (n) ... = n bytes read = Checksum User data starts at logical address 0x00 0x86 Read User Data Physical Successful = 0x86 = tag type = number bytes successfully read (n) ... = n bytes read = Checksum = 0x90 = tag type = number bytes successfully read (n) ... = n bytes read = Checksum UID starts at logical address 0x00 to 0x07 Lock bits start at logical address 0x08 to 0x09 OTP bits start at logical address 0x0A to 0x0F User data starts at logical address 0x10 0x8F Read Error = 0x8F = Error code: 1 byte = Checksum = 0xA0 = tag type = number bytes successfully written = Checksum
0x90
Read UID/Lock/OTP/User Data Logical Successful
0xA0
Write User Data Logical Successful
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0xA4
Explanation Write User Data Logical to specific UID Successful
Bytes = 0xA4 = tag type = number bytes successfully written = Checksum = 0xA6 = tag type = number bytes successfully written = Checksum = 0xA8 = tag type = number bytes successfully written = Checksum = 0xB0 = tag type = number bytes successfully written = Checksum
0xA6
Write Physical Successful
0xA8
Write Physical to specific UID Successful
0xB0
Write Lock/OTP/User Data Logical Successful
0xB4
0xAF
Write Lock/OTP/User Data Logical to specific = 0xB4 UID = tag type = number bytes successfully written Successful = Checksum Write Error = 0xAF = Error code: 1 byte = Checksum
0xBA
Built-In Self Test Response (See Built-In self test section for further details).
= 0xBA = Test Result ... = Software Version: 2 bytes Serial Number/Production Information: 8 bytes = Checksum
Tag Type 0x44 0x0C Error Code 0x10 0x11 0x12 0x13 0x14 Explanation Verify error during write Wrong serial number tag present for specific write Area to be written is locked Start address out of range Write size exceeds tag capacity Explanation Mifare Ultralight Innovision Jewel
See Appendix B for an example Command Response sequence. 19
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Sleep-Mode
The AT90RF135602 will enter low quiescent current "Sleep Mode" when /SS is high and all tag operations have been completed.
SPI Clock Frequency
This is determined by the host micro-controller, since this is the master and hence will generate the SCK signal. The recommended SPI clock frequency is 115kHz.
Power On Reset, Reset & Host In-circuit Programming
Power On Reset (POR) From cold start the POR will occur followed by initialisation of the microprocessor. From application of power the AT90RF135602 will be ready to receive an SPI command data within 6 mS. The active low /RESET signal from the host will cause the AT90RF135602 to enter the reset condition. From release of this signal high the AT90RF135602 will be ready to receive SPI command data within 6 mS. When /RESET is held low the AT90RF135602 will enter serial programming mode. In this mode the SPI SCK, MISO, MOSI lines may be used to upgrade the firmware.
Reset
Built-In Self Test (BIST) Mode
General The BIST consists of a single sequence of test stages designed as a confidence test that the AT90RF135602 is operational and also as a basic diagnostic aid if operation becomes impaired. Beyond this it is not possible to perform an exhaustive test of operational performance without the presence of a tag for functional test purposes. The BIST mode is activated by the single byte Host SPI command 0x70. BIST Sequence: * * CRC Verification of all Flash Program Memory If this test fails, subsequent tests are not performed. Integrity of all RAM Memory If this test fails, subsequent tests are not performed. * Loop around Test
Initiation
The Loop around Test is designed to test the Xtal oscillator, antenna drive and demodulator sections of the AT88RF135602 for connectivity and operation to a limited functional extent.
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BIST Response
The BIST response is composed of 12 bytes followed by a checksum. The structure of the response is shown in following table:
Byte 1
Name Built-In Self Test response
Description 0xBA The test result byte indicates the progress of the self-test. Test errors are indicated in a bitwise fashion as listed below:
2
Test Result
0x00 : All tests passed 0x01 : Flash CRC verification problem 0x02 : RAM integrity problem 0x04 : Loop back problem
3-4 .... 5-12 .... Serial number and production information 8 bytes, (MSB first), representing the serial number and production information stored in EEPROM. Software Version 2 byte (MSB first) data representing the software version of the application in Flash Memory. For example 0x02, 0x07 represents version V2.7
An example of the BIST response is shown below
0xBA, 0x00, 0x02, 0x07, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88 0xBA: 0x00: BIST Response Successful test result
0x02,0x07: Software Version 2.7 0x11,0x22,0x33,0x44: Serial/Production Information 0x11223344 0x55,0x66,0x77,0x88: Serial/Production information 0x55667788
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Appendix A - Tag Memory Maps
A1 Mapping Between Logical Address & Philips Mifare Ultralight Physical Memory
Logical Address for user data only; 0x80 0xA0 0xA4 0-3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 32-35 36-39 40-43 Physical Address Description
Logical Address for; 0x90 0xB0 0xB4 0-2 3-6 7 8-9 10-13 14-15 16-19 20-23 24-27 28-31 32-35 36-39 40-43 44-47 48-51 52-55 56-59
Page
Byte Number
Name
Comments
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
0-2 0-3 2-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3 0-3
SN0 - SN2 SN3 - SN6 Lock0-Lock1 OTP0 - OTP3 Data0 - Data3 Data4 - Data7 Data8 - Data11 Data12 - Data15 Data16 - Data19 Data20 - Data23 Data24 - Data27 Data28 - Data31 Data32 - Data35 Data36 - Data39 Data40 - Data43
Serial Number (UID) Serial Number (UID) Lock Bytes OTP - writes are bit-wise "ored" with existing contents User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write
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A2 Mapping Between Logical Address & Innovision Jewel Physical Memory
Logical Address for user data only; 0x80 0xA0 0xA4
-
Logical Address for; 0x90 0xB0 0xB4
Physical Address
Description
Block (Hex)
Byte Number
Name
Comments
0-7
0
0-7
UID0 - UID7
Unique identification Number (used to verify correct tag is the target of read/write commands) Lock Bytes OTP - writes are bit-wise "or-ed" with existing contents User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write User Data area - read/write
0-7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 64-71 72-79 80-87 88-95
8-9 10-15 16-23 24-31 32-39 40-47 48-55 56-63 64-71 72-79 80-87 88-95 96-103 104-111
E E 1 2 3 4 5 6 7 8 9 A B C
0-1 2-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7 0-7
LOCK0 - LOCK1 OTP0 - OTP5 Data0 - Data7 Data8 - Data15 Data16 - Data23 Data24 - Data31 Data32 - Data39 Data40 - Data47 Data48 - Data55 Data56 - Data63 Data64 - Data71 Data72 - Data79 Data80 - Data87 Data88 - Data95
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A3 Lock Bit Functionality This section outlines the operation of the lock bits located at logical address 8 & 9 for
commands 0x90, 0xB0, 0xB4. The Lock bits are used to `write protect' blocks of memory. For example, bit 0 of lock byte 0 locks the first 8 data bytes (addresses 0x10 to 0x17 for commands 0x90, 0xB0, 0xB4) Bit 1 of lock byte 0 locks the second block of 8 data bytes (addresses 0x18 to 0x1F for commands 0x90, 0xB0, 0xB4) The correlation between lock bits and areas of logical memory locked is shown in the table below:
Lock Byte 0
Bit Memory locations locked (decimal) MSB - 7 56 - 63* 6 48 - 55* 5 40 - 47 4 32 - 39 3 24 - 31 2 16 - 23 1 08 - 15 LSB - 0 00 - 07
0x80, 0x84, 0xA0, 0xA4 commands 0x90, 0xB0, 0xB4 commands
72 - 79*
64 - 71*
56 - 63
48 - 55
40 - 47
32 - 39
24 - 31
16 - 23
Lock Byte 1
Memory locations locked (decimal) MSB - 7 0x80, 0x84, 0xA0, 0xA4 commands 0x90, 0xB0, 0xB4 commands unused unused unused unused 104 -111* 96 - 103* 88 - 95* 80 - 87* unused unused unused unused 88 - 95* 80 - 87* 72 - 79* 64 - 71* 6 5 4 Bit 3 2 1 LSB - 0
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Appendix B - Command Examples
B1 Command Response Sequence Example 1
To read 3 bytes of data starting from logical address DATA4: Command, = 0x80 Start address, = 0x04 Data length value, = 0x03 Checksum, = 0x87 WITH TAG PRESENT Initiate Read; C1: R1: <80><04><03><87> <00><00>
Poll status; C2: R2: <00><00> <01><01>AT90RF135602 is busy
Poll status; C3: R3: <00><00> <01><01>AT90RF135602 is busy
Poll status; C4: R4: <00><00> <80><44><03><44><55><66> Read successful
Response = 0x80 Tag type = 0x44 (Mifare Ultralight) Number of bytes successfully read = 0x03 Data4=0x44, Data5=0x55, Data6=0x66 Checksum = 0xC6
B2 Command Response Sequence Example 2
To read 3 bytes of data starting from logical address DATA4: Command, = 0x80 Start address, = 0x04 Data length value, = 0x03 Checksum, = 0x87 NO TAG PRESENT Initiate Read; C1: R1: <80><04><03><87> <00><00>
Poll status;
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4407A-SCR-04/05
C2: R2:
<00><00> <01><01>AT90RF135602 is busy
Poll status; C3: R3: <00><00> <01><01>AT90RF135602 is busy
Poll status; C4: R4: <00><00> <20><20> No tag found
Status = 0x20 Checksum = 0x20
B3 Command Response Sequence Example 3
To write 4 bytes of data, starting from logical address DATA5: Command, = 0xA0. Start address, = 0x05. Data length value, = 0x04. DATA5 = 0x55, DATA6 = 0x66, DATA7 = 0x77, DATA8 = 0x88. Checksum, = 0x63. WITH TAG PRESENT Initiate Write; C1: R1: <05><04><55><66><77><88><63> <00><00>
Poll status; C2: R2: <00><00> <01><01>AT90RF135602 is busy
Poll status; C3: R3: <00><00> <01><01>AT90RF135602 is busy
Poll status; C4: R4: <00><00> <44><04> Write successful
Response = 0xA0 Tag Type = 0x44 Number of bytes successfully written = 0x04 Checksum = 0xE8
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Electrical Characteristics
Absolute Maximum Ratings
Note: I = industrial ........................................................-40C to 85C Operating Temperature................................... -30C to + 80C StorageTemperature ....................................... -40C to + 85C Voltage on VCC to VSS ......................................-0.5V to + 6.5V Voltage on Any Pin to VSS ..........................-0.5V to VCC + 0.5V Power Dissipation Typical........................................... 120 mW Power Dissipation Max ............................................... 300 mW Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Power dissipation is based on the maximum allowable die temperature and the thermal resistance of the package.
DC Parameters
Symbol ICC ICC Power Down ICC Active (field off) ICC Active (field on) IOL/H Parameter Supply voltage Sleep mode current consumption Operating current Transmitting current Output current at Tx1 or Tx2 Output resistance at Tx1 or Tx2 Drive level 1 Drive level 2 Drive level 3 Drive level 4 Rise and fall time for 100% ASK Xtal frequency range Ext clock Xin Rx input resistance Rx input capacitance Rx input delta carrier envelope change Rx input envelope amplitude VIL VIH VOL VOH Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL=10mA Vcc=2.7V IOH=-10mA Vcc=2.7V 2.2 1 -0.5 0.6Vcc 2 0.3Vcc Vcc+0.5 0.5 13 1 8.8 11 4 13.56 14 Vcc 13.2 Max drive level -100 40 20 10 5 S MHz V (p-p) k pF mV p-p V p-p V V V V Conditions Min 2.7 Typ 2.8 1uA 6.6 40 65 100 Max 3.0 10uA Unit V A mA mA mA
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AC Parameters
Figure 8. Power Characteristics
2 Waveform State active :~6.7mA sleep - ~1uA* 2.8V high high low low 0V 1
3
Note:
1. Sleep current is n~1uA with the PC3-Xin link and ~36uA without the link, (operational mode set appropriately)
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on 1.0 July 2004
Line Power Vcc
Power Consumption
Slave Select __ SPI SS
_____ RESET
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Figure 9. SPI Characteristics
State
Waveform 9
Line Slave Select 4 8
high
/SS
low
Clock 6 5 7
SCK
high
low
29
Figure 10. Command Execution Characteristics
30
Waveform Tag Read Read Command Read Data transfer 10 11 12
Line Slave Select
State
/SS
high
low
Clock
SCK
high
low
Power Consumption
tag communication - ~40mA
host communication - ~6.7mA
sleep ~ 1uA
4407A-SCR-04/05
Table 2. Interface Timing Parameters
Id 1 2 3 4 5 6 Description AT90RF135602 Cold Power up time SPI /SS low to exit from sleep mode (warm power up time) SPI /SS high to entry into sleep mode SPI /SS low to SPI SCK high SPI SCK Period SPI Data Rate Min (s) 3 3.2 poll : 40 non-poll : 50 poll : 10 non-poll : 23 6 3 Typical 498 ms 20 us 20 us Max (s) -
7 8 9 10 11 12
SPI LSB to MSB period SPI SCK low to SPI /SS high SPI /SS high time transmission of command 0x80 to read 16 bytes Reading 16 bytes from mifare ultralight tag polling the response to the read /SS high to MISO tri-state /SS low to MISO output
0.8 ms 8.0 ms 1.3 ms
-
-
10 ns 15 ns
-
Note:
1. "-" No value applicable 2. The AT90RF135602 will enter its power saving sleep mode when the /SS line is inactive (high) and any tag read/write operation has been completed. 3. The AT90RF135602 will exit its sleep mode when /SS goes active (low). 4. The Host should maintain /SS active only for the duration of the communication, this allows the AT90RF135602 to know when it is safe to enter sleep mode or when its SPI transmission buffer may be updated. 5. The AT90RF135602 will tri-state the MISO line when /SS is high. 6. The AT90RF135602 will enter serial programming mode if /RESET is held low.
_____ RESET low high high high low
__ SS Reserved SPI interface sleeping MISO tri-state SPI interface active Interface Mode
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Ordering information
Supply Part Number AT90RF135602-7MTUL Voltage (V) 2.7 - 3.3 Temperature Range Industrial Package LBGA36 Packing Tray Green Compliance Yes
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Packaging Information
LBGA 36 Pin
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4407A-SCR-04/05
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